The present invention relates generally to a system and method for fabricating integrated circuits (xe2x80x9cICxe2x80x9ds), and more particularly to an integrated circuit comprising a small planar area memory cell with a SELF ALIGNED trench and vertical transistor, and method of forming thereof.
The semiconductor industry is continuously trying to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today""s semiconductor products. For example, it is not uncommon for there to be millions of semiconductor devices on a single semiconductor product.
Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device, and devices have approached sizes down to tenths of microns and less. There is some limit, however, as to how far a horizontally oriented semiconductor device can be shrunk, and as devices are made even smaller, it is generally becoming increasingly difficult to further miniaturize a device""s horizontal dimensions. In addition, the decreasing horizontal dimensions of semiconductor devices generally tend to create problems in the operational characteristics of the semiconductor devices.
One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor memory is a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). A DRAM may include millions or billions of individual DRAM cells, each cell storing one bit of data. A DRAM memory cell typically includes an access field-effect transistor (xe2x80x9cFETxe2x80x9d) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Semiconductor memory density is typically limited by a minimum feature size F, that is imposed by processes (e.g., lithographic) used during fabrication. The planar area of current prior art devices is typically about 8 F2. There is a continuing need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs.
One way of increasing the data storage capacity of semiconductor memories is to reduce the amount of integrated circuit horizontal planar area consumed by each memory cell. For horizontally oriented devices, this may be done by decreasing the size of the access FET or the storage capacitor, or both. This approach has limits, however, due to minimum producible structure size in a given fabrication technology, and the problems associated with devices with small dimensions, such as hot carriers, punch through, and excess leakage.
A different approach to providing planar area reduction is the use of a three-dimensional arrangement of the access FET and the storage capacitor. One such arrangement is a planar FET next to a deep trench capacitor. The trench capacitor has plates which are located vertically along the walls of the trench instead of being parallel to the surface of the integrated circuit substrate. This permits a large capacitance per planar unit area of substrate, while at the same time allowing the device to be of a manageable size for purposes of operation.
Further reduction in the amount of planar area required for each cell, may be achieved by using a vertical trench transistor in conjunction with a vertical trench capacitor in a memory cell. In a typical design, the vertical capacitor is generally fabricated in a trench, with one conductive plate being formed in the substrate, the dielectric being formed on the trench sidewalls, and the other conductive plate being formed in the interior of the trench. A vertical trench transistor is generally fabricated adjacent to an upper portion of the trench, with the source and drain being fabricated in the substrate, and the vertically-oriented gate being fabricated in the trench.
Alternatively, a vertical transistor may be paired with a stack capacitor in a memory cell. In a typical design, the vertical trench transistor may have a vertically-oriented gate being fabricated in the substrate, and the stack capacitor may be formed above the vertical transistor. A stack capacitor generally utilizes a three-dimensional structure at the surface of or on the substrate, as opposed to being formed in a trench under the substrate surface like a trench capacitor.
There are generally several problems, however, with prior art approaches to fabricating a smaller planar area DRAM cell. One difficult fabrication issue is that several lithographic/mask steps are used in typical prior art methods. As an example, there may be masks associated with forming a deep trench, forming an active area, and forming a gate. Generally, the more mask steps involved, however, the less robust and the lower the yield of the overall process. Each mask step poses a risk of misalignment between the mask and the device in process. Generally, mask alignment is especially critical when working with features with a high aspect ratio, height to width, as with a deep trench.
These problems are generally solved or circumvented, and technical advantages are generally achieved, by a preferred embodiment of the invention in which a trench for a DRAM cell is formed with a substantially SELF ALIGNED process. The trench, active area, and gate of a DRAM cell may be formed using a minimal number of masks and lithographic steps. Using this process, a DRAM cell comprising a vertical transistor and a buried word line may be formed. A gate dielectric may be disposed adjacent the active area, and the portion of the buried word line adjacent the gate dielectric may function as the vertically oriented gate for the vertical transistor. The DRAM memory cell may comprise one of a variety of capacitors, such a trench capacitor underlying the vertical transistor, or a stack capacitor overlying the vertical transistor. When a stack capacitor is used, a buried bit line underlying the vertical transistor may also be used.
In accordance with a preferred embodiment of the present invention, a method of forming vertically oriented semiconductor devices in an integrated circuit comprises forming substantially parallel first elongated trenches in a semiconductor region; filling the first elongated trenches with an insulator to form isolation lines; forming substantially parallel second elongated trenches in the semiconductor region, wherein the second elongated trenches cross and are substantially perpendicular to the first elongated trenches, and wherein pillars of the semiconductor region are formed between the elongated trenches; forming active areas for the vertically oriented devices in the pillars; and forming elongated buried word lines in the second elongated trenches, wherein portions of the word lines adjacent the active areas also form vertically oriented gates for the vertically oriented devices.
In accordance with another preferred embodiment of the present invention, an integrated circuit comprises first substantially parallel elongated trenches disposed in a semiconductor region; isolation lines disposed in the first elongated trenches; second substantially parallel elongated trenches disposed in the semiconductor region, wherein the second elongated trenches cross and are substantially perpendicular to the first elongated trenches, and wherein pillars of the semiconductor region are located between the elongated trenches; vertically oriented devices comprising active areas disposed in the pillars; and elongated word lines disposed in the second elongated trenches, wherein portions of the word lines adjacent the active areas are also vertically oriented gates for the vertically oriented devices.
An advantage of a preferred embodiment of the present invention is that a SELF ALIGNED trench structure may be formed for use in a DRAM cell. For example, a DRAM may be fabricated with a SELF ALIGNED trench, active area and gate.
Another advantage of a preferred embodiment of the present invention is that smaller device cells may be realized for a DRAM. For example, a cell size of 2 Fxc3x972 F, or 4 F2 is possible using the teachings of the present invention.
Another advantage of a preferred embodiment of the present invention is that different types of capacitors, such as trench or stack, may be used depending on the requirements of the specific application.
Another advantage of a preferred embodiment of the present invention is that at least the initial processing may be performed on a long trench instead of isolated individual holes, thus providing a larger planar area and easier access for subsequent processing.
Another advantage of a preferred embodiment of the present invention is that a buried word line may be formed in the long trench, leaving the surface of the structure clear for other device elements.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.